AAS supports various types of verification environments:

Co-Simulation
- SV-PY:  SystemVerilog-Python co-sim. Reference model implemented in Python
- SV-C: SystemVerilog-C co-sim. Tests are written in C, DUT contains CPU.

Verification Strategy
- Random Coverage Driven - Sign-off is based on key coverage metrics, including functional and code coverage. Both random and directed tests are used. 
- Tests Driven - Test scenarios are defined based on a feature list to ensure coverage of all features.  

Verification Capabilities